1. Field of the Invention
This invention relates to a communication system comprising a network of interconnected transceivers and associated digital systems and, more particularly, to mechanisms for selectively clocking the digital systems, bypassing data from being routed through the digital systems, or for reducing power consumption within transceivers and digital systems depending on whether data is received by the transceiver, and/or whether the transceivers are locked in sync with the data.
2. Description of the Related Art
Communication systems are generally well-known as containing at least two nodes interconnected by a communication line. Each node may include both a transmitter and a receiver, generally referred to as a xe2x80x9ctransceiverxe2x80x9d. The transceiver provides an interface between signals sent over the communication line and a digital system which operates upon that signal in the digital domain.
A set of nodes interconnected by a communication line can be referred to as a communication network. A transmitter within one node can transmit a signal to one or more receivers in various nodes across the network. In high speed applications, the signal transmitted across the network can contain instructions and/or data, which conceivably could be audio data, video data, or both, and therefore the network may be considered a multi-media network. The transfer rate of multi-media signals is generally quite high and therefore requires a relatively high speed communication line, a suitable line being an optical fiber, for example.
If an optical fiber is used, then an interface which converts light energy to an electrical signal recognized by each transceiver is needed. That interface is generally a photosensor at the receive end of the communication line, or a light emitting diode at the transmit end. The interface is therefore an optical interface and therefore the transceiver can be considered a fiber optic transceiver. It is believed that most conventional fiber optic transceivers generally encompass elements which perform light/voltage conversion and nothing else. The system associated with each transceiver may employ both an analog and a digital section which perform manipulation of the received signal, processes that signal, and thereafter presents a transmitted signal compatible with signals forwarded across the optical fiber. Accordingly, a conventional, optical multi-media network typically employs a rather simplistic fiber optic transceiver, and a digital processing system, at each node of the network.
The digital system may be called upon not only to process the signal preferably in real-time, but also to process those signals synchronously. Therefore, conventional digital systems not only require a receiver with accurate amplification and data detection, but further utilize a phase-locked loop (xe2x80x9cPLLxe2x80x9d) useful in recovering a clocking signal from the received data. If the amplifiers and data detecting circuits at the receive end, drivers at the transmit end, and the PLL clock recovery circuits impute noise to, or receive noise from, the digital core of the digital processor, then data detection, clock recovery, data transmittal, and generalized data processing may be adversely affected. It would be desirable to minimize the cross talk between the digital processing core and the incoming data detection, clock recovery, and outgoing data driving circuits. Digital signal transitions, and/or latching circuits operating on those transitions, can oftentimes induce significant amounts of noise upon the power and ground conductors extending across the digital system to provide power and ground to the more sensitive clock and data recovery circuits, as well as the data transmit driver.
In addition to minimizing noise susceptibility of the sensing circuits, it would also be of benefit to provide power management to at least a portion of those circuits. In this manner, a low-power application can be realized as a significant improvement to conventional multi-media communication networks. Coupled with noise isolation and power management, the sensing portion of each node should also be made immediately responsive to the data signal forwarded from the network master. In this fashion, the slave nodes can recover a clocking signal in parallel and concurrent with each other so that the clocking signal is available as soon as possible to the corresponding digital systems.
The problems outlined above are in large part solved by an improved multi-media communication system. The communication system includes a set of nodes, wherein each node involves a transceiver interface and a digital system. The transceiver is coupled between the communication line and a corresponding digital system, and is used to modify the transmission format and/or protocol into a sequence of bits recognized by one or more digital systems within corresponding nodes. The transceiver is purposely placed on one or more monolithic substrates separate from a substrate bearing a digital system. The sensitive sensing and driving circuits, as well as the clock recovery PLL, may be embodied upon the transceiver separate from the corresponding digital system, and the noise induced by that system.
The present transceiver includes both a receiver and a transmitter. The receiver senses data transmitted across the communication line and performs conditioning and amplification to that signal before transferring it to the digital system for processing. Additionally, the receiver may include a PLL which recovers a clock from the received signal, and uses the recovered clocking signal to synchronize operations within the corresponding digital system. Of benefit, the number of conductors which link the transceiver and corresponding digital system is minimized as, for example, a data output conductor, a clocking/status signal output conductor, power, and ground. The power and ground conductors may be used to apply a common VDD and VSS supplies between the transceiver and corresponding digital system. It is noted, however, if a common power and ground supply is not needed, then only two conductors need be employed between the receiver of the transceiver and the respective digital system.
The sensing circuitry within the receiver generally operates at speeds matching the incoming data. For example, if the data rate of the incoming signal, and therefore the operating speed of the sensing circuitry, is several Mbits/second, or more preferably 50 Mbaud or greater, then the power consumed by the sensing circuitry can be rather substantial. Instead of maintaining power to the sensing circuitry during times when a signal is not present on the communication line, the receiver utilizes an activity detector which de-couples power to the sensing circuit in times when data is not present on the receiver receive port. In this manner, the present transceiver maintains power to power consumptive devices only when an input signal is present upon the receive port. During all other times, the power consumptive amplifiers, comparators, and clock recovery circuits (i.e., PLL) are powered down. Thus, a multi-media network employing the present transceivers can advantageously be placed in a low power environment, or an environment in which power is drawn from a portable power supply, such as a battery. For example, the multi-media network can be used in an automotive application, where audio, video, or generalized traffic information, are being sent between digital processors arranged throughout the automobile. Such processors include, for example, speech encoders/decoders, video/audio processors, video monitors, audio amplifiers (and associated speakers), sensors, calculators, computers, and FM/AM tuners, all of which can be placed on-board existing automobiles to enhance both usability and performance of the automobile. In an automotive environment, it is desirable that the communication line be fiber optic, and the light-transmissive data be isolated from each transceiver by photosensors and LEDs. Optical fibers can accommodate the relatively high baud rates of the multi-media network, but also can reliably send those rates to nodes distally located from one another at various locations about the automobile.
A transceiver which is isolated on one or more chips separate from the noisy digital systems, and which contains receive-sensing circuitry and clock recovery mechanisms is henceforth referred to as a xe2x80x9csmartxe2x80x9d transceiver. The smart transceiver contains active and passive components which can, in addition to its sensing, driving, and clock recovery functions, also selectively powers certain components only when incoming data is present on the receive port. The smart transceiver therefore has power management capability and, furthermore, can selectively bypass the digital system connected to the transceiver. The digital system is bypassed at times when the input signal is present upon the receive port, yet clock recovery (i.e., PLL xe2x80x9clockedxe2x80x9d status) has not yet occurred.
The bypass feature occurs whenever, for example, input data in the form of optical energy is received upon the receive port of the transceiver, yet time has not sufficiently elapsed to allow the PLL to lock its voltage-controlled oscillator (xe2x80x9cVCOxe2x80x9d) output to the incoming data stream transitions. In a network environment, the network is arranged having a plurality of nodes typically configured in a ring. The first node slave within the ring will then initially receive an incoming signal from a master. Rather than waiting for that node""s transceiver PLL to lock upon the incoming data stream frequency and phase, the first node receiver simply forwards the unlocked data stream signal from the receiver output to its transmitter input, whereupon the first node transmitter output will then be immediately dispatched to the next node within the network. That node will perform the same bypass operation, thereby allowing all nodes within the network to receive somewhat in parallel the incoming optical signal. This affords the PLL in each node to lock upon the incoming light stream at approximately the same time, thereby achieving relatively concurrent locking among all clock recovery PLLs within each network node. Thereafter, once valid data is sent across the network, any node within that network will be able to immediately recognize and process the valid data since each and every node will have a pre-existing, recovered clocking signal.
According to one embodiment, a communication system is present. The communication system includes a plurality of digital systems interconnected by respective transceivers to a communication line. At least one of the transceivers comprises a receiver adapted to enter a relatively high power consumptive state from a relatively low power consumptive state during times when a signal is present within the communication line. When the signal is absent, the receiver transitions from the high power consumptive state to the low power consumptive state. The receiver includes a PLL and incoming data sensing circuits. The PLL produces a clocking signal and forwards the clocking signal to a respective digital system when the PLL is locked in sync with transitions of the incoming signal. When the incoming signal is present yet the PLL is not yet locked in sync with that signal, the PLL will produce a clocking signal at a reduced clocking frequency to protect against overdriving the digital system connected to receive that clocking signal. Therefore, at times in which the PLL is in an unlocked state, it can be assured that the digital system will not be driven at a rate which exceeds the maximum frequency at which it can operate.
According to another embodiment, the digital system can include a lock detector which bypasses forwarding the incoming signal sent to the receiver, through the receiver, and to the digital system. Instead, the lock detector will forward the incoming signal directly to a transmitter whenever the PLL is not locked in sync with that incoming signal.
According to yet another embodiment, a receiver is provided having a receive port and an activity detector coupled to the receive port. The activity detector produces an activity signal during times when an input signal is forwarded to the receive port. A power supply generator is coupled to the activity detector which then produces a power supply output upon receipt of the activity signal. Coupled to the power supply generator and the receive port is a receiver that comprises receive/sensing circuitry, and preferably a PLL. The PLL produces a clocking signal from the input signal during times when the power supply output is produced. The activity detector includes, for example, a comparator and a timer, both of which work in conjunction to produce the activity signal if a magnitude of the input signal upon the receive port exceeds a reference voltage for a defined amount of time. A lock detector can be attributed to (i.e., embodied upon ) the digital system or, alternatively, attributed to the transceiver. In the latter instance, the lock detector is output from the transceiver and forwarded to a multiplexer coupled to select the input signal for transmission to a transmitter in lieu of an output from the digital system if the detector yields an unlock value.
According to yet a further embodiment, a method is provided for regulating power consumption within, and clocking signal output from, a transceiver. While maintaining power needed to detect if and when an input signal is forwarded to the transceiver, power is de-asserted to sensing and calibration circuitry of the receiver which receives the input signal, as well as de-asserting power to a PLL within the receiver whenever an input signal is absent from a receive port of the receiver. A clocking signal can be produced from the PLL by asserting power to the PLL only when the input signal is present. It is understood that the PLL is preferably a part of the receiver; however, the PLL can be part of the digital system and the receiver merely generates a status signal to the power supply generator depending on whether the PLL is to receive power. The state of the status signal is thereby dependent on whether activity is detected in the network via the input signal.